The present invention relates to a level shift circuit usable in a semiconductor device which operates internally at a low voltage.
LSIs (Large-Scale Integrated circuits) have been advancing toward higher speeds and higher integrations with the progress of microfabrication techniques. Low power consumption of LSIs is one of key techniques for practical use of LSIs that operate at high speed. For high-speed operation of these LSIs, because larger power consumption is involved, ceramic packages are adopted for stable operation, or radiation fins and the like are necessitated, which poses a problem that the cost increases. Also, in the case of small-size, lightweight portable equipment which is popular these days, low power consumption is of importance from the point of view of running time of batteries as well.
Although lowering the operating voltage is very effective in lowering the power consumption of an LSI, there is a need of enlarging input/output signal swings in order that signal exchange with other LSIs is enabled even if internal operating voltage VDD is lowered, in which case a level shift circuit for enlarging signal swings is necessitated.
A conventional LSI that operate with low voltage is provided with a level shift circuit shown in FIG. 10, which interfaces externally with a voltage higher than the LSI""s internal voltage. This level shift circuit, as shown in FIG. 10, has: an N-channel MOS (Metal Oxide Semiconductor) field effect transistor (hereinafter, referred to as NMOS transistor) N101 to the gate of which an input signal A is supplied and the source of which is connected to the ground GND; a P-channel MOS field effect transistor (hereinafter, referred to as PMOS transistor) P101 the drain of which is connected to the drain of the NMOS transistor N101 and to the gate of which the input signal A is connected; an NMOS transistor N102 to the gate of which the input signal A is connected and the source of which is connected to the ground GND; an NMOS transistor N103 the gate of which is connected to the drain of the NMOS transistor N101 and the source of which is connected to the ground GND; a PMOS transistor P102 the gate of which is connected to the drain (node 102) of the NMOS transistor N103 and the drain of which is connected to the drain (node 101) of the NMOS transistor N102 and the source of which is connected to power supply VCC; and a PMOS transistor P103 the gate of which is connected to the drain (node 101) of the NMOS transistor N102 and the source of which is connected to the power supply VCC and the drain of which is connected to the drain (node 102) of the NMOS transistor N103. The NMOS transistor N101 and the PMOS transistor P101 constitute an inverter circuit IV100, and this inverter circuit IV100 operates with internal power supply VDD ( less than VCC) connected to the source of the PMOS transistor P101 and outputs an inverted signal of the input signal A. Then, the level shift circuit shifts the level of the input signal A to produce an output signal Y having a swing larger than that of the input signal A.
However, when a large level shift amount is involved, for example, when a swing of 0.5 V is changed to a swing of 3.3 V, because the driving current of the MOS transistor that operates at 0.5 V is small, the delay time of the circuit is increased, causing a problem of lowered operating speed of the circuit. As a solution to it, it is conceivable to lower the threshold, voltage Vth of the MOS transistor so that the driving current of the MOS transistor does not become so small even at low voltage. However, lowering the threshold voltage Vth would cause the leak current of the MOS transistor to increase, posing a problem that the power consumption increases due to the leak current even in the standby mode. Also, employing a microfabrication process in which the gate oxide is reduced in film thickness to increase the driving current of the MOS transistor that operates at 0.5 V would lead to a problem that the transistor would not be able to endure a voltage of 3.3. V, leading to breakdown.
Therefore, an object of the present invention is to provide a level shift circuit capable of realizing low power consumption without lowering the operating speed at a low voltage, while securely preventing the breakdown with ease.
In order to accomplish the above object, according to a first aspect of the present invention, there is provided a level shift circuit for providing an output signal having a swing larger than a swing of an input signal, the level shift circuit including a plurality of MOS transistors constituting a circuit operative at a low voltage and a circuit to which a voltage higher than the low voltage is applied, wherein among the plurality of MOS transistors, at least one of MOS transistors to gates of which a signal having a swing corresponding to the swing of the input signal is supplied is a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Note here that the words xe2x80x9cchannel forming semiconductor regionxe2x80x9d of a MOS transistor refers to a semiconductor region where a channel is to be formed when the transistor is turned on.
Also, there is provided a level shift circuit, according to a second aspect of the present invention, for providing an output signal having a swing smaller than a swing of an input signal, the level shift circuit including a plurality of MOS transistors constituting a circuit operative at a low voltage, wherein at least one of the plurality of MOS transistors is a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Also, there is provided a level shift circuit according to a third aspect of the invention, comprising:
an inverter circuit having a first first-conductivity-type MOS transistor and a first second-conductivity-type MOS transistor connected complementary to each other between a first power supply and a ground, the inverter circuit providing an inverted signal of an input signal;
a second first-conductivity-type MOS transistor to a gate of which the input signal is connected and a source of which is connected to the ground;
a third first-conductivity-type MOS transistor to a gate of which an output of the inverter circuit is connected, and a source of which is connected to the ground;
a second second-conductivity-type MOS transistor whose gate is connected to a drain of the third first-conductivity-type MOS transistor, and whose source is connected to a second power supply, and whose drain is connected to a drain of the second first-conductivity-type MOS transistor; and
a third second-conductivity-type MOS transistor whose gate is connected to the drain of the second first-conductivity-type MOS transistor, and whose source is connected to the second power supply, and whose drain is connected to the drain of the third first-conductivity-type MOS transistor, wherein
the first first-conductivity-type MOS transistor and the first second-conductivity-type MOS transistor of the inverter circuit, and the second and third first-conductivity-type MOS transistors are each a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Furthermore, a level shift circuit of a fourth aspect of the invention comprises an inverter circuit having a first-conductivity-type MOS transistor and a second-conductivity-type MOS transistor connected complementary to each other between a power supply and a ground, the inverter circuit providing an inverted signal of an input signal, the inverted signal shifted in level to a swing smaller than a swing of the input signal, wherein either one of the first-conductivity-type MOS transistor or the second-conductivity-type MOS transistor of the inverter circuit is a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Still further, there is provided a level shift circuit according to a fifth aspect of the invention comprising:
an inverter circuit having a first first-conductivity-type MOS transistor and a first second-conductivity-type MOS transistor connected complementary to each other between a first power supply and a ground, the inverter circuit providing an inverted signal of an input signal;
a second first-conductivity-type MOS transistor to a gate of which the input signal is connected, and a source of which is connected to the ground;
a third first-conductivity-type MOS transistor whose gate is connected to an output of the inverter circuit, and whose source is connected to the ground;
a second second-conductivity-type MOS transistor whose gate is connected to a drain of the third first-conductivity-type MOS transistor, and whose source is connected to a second power supply, and whose drain is connected to a drain of the second first-conductivity-type MOS transistor; and
a third second-conductivity-type MOS transistor whose gate is connected to the drain of the second first-conductivity-type MOS transistor, and whose source is connected to the second power supply, and whose drain is connected to the drain of the third first-conductivity-type MOS transistor, wherein
the second and third second-conductivity-type MOS transistors are each a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
In the level shift circuit of each of the first to fifth aspects of the invention, the first-conductivity-type may be one of P-channel type and N-channel type and the second-conductivity-type may be the other of the P-channel type and N-channel type.
In the level shift circuit of the third aspect of the invention, if the first-conductivity-type is the N-channel type and the second-conductivity-type is the P-channel type, the levels of the first power supply, the second power supply and the ground may be: second power supply level greater than first power supply level greater than ground level. On the other hand, if the first-conductivity-type is the P-channel type and the second-conductivity-type is the N-channel type, the levels of the first power supply, the second power supply and the ground may be: second power supply level less than first power supply level less than ground level.
In the level shift circuit of the fifth aspect of the invention, if the first-conductivity-type is the N-channel type and the second-conductivity-type is the P-channel type, the levels of the first power supply, the second power supply and the ground may be: first power supply level greater than second power supply level greater than ground level. On the other hand, if the first-conductivity-type is the P-channel type and the second-conductivity-type is the N-channel type, the levels of the first power supply, the second power supply and the ground may be: first power supply level less than second power supply level less than ground level.
In the level shift circuit of each of the first to fifth aspects of the invention, in the process of turning on the MOS transistor whose channel forming semiconductor region is electrically connected to the gate, the voltage of the channel-forming semiconductor region increases with the increasing gate voltage, so that the threshold voltage for the MOS transistor lowers and the driving current increases. When this MOS transistor is turned off, the threshold voltage is maintained, as in the ordinary MOS transistors, so that the leak current is suppressed. That is, in the MOS transistor with the channel forming semiconductor region electrically connected to the gate, the threshold voltage dynamically changes. According to the invention, by using such a MOS transistor having a dynamically changing threshold voltage, it is possible to obtain a large driving current even at a low voltage, while suppressing leak currents. Thus, there can be provided a level shift circuit in which low power consumption can be realized without lowering the operating speed at a low voltage. Also, by using the MOS transistor in which the threshold voltage dynamically changes, the on-resistance of the MOS transistor can be reduced without increasing gate length or gate width, so that the circuit area can be made smaller than a conventional circuit.
The level shift circuit according to any one of the first to fifth aspects may be built into a semiconductor device (such as a system LSI) which operates internally at a low voltage. In this case, there can be provided a highly reliable semiconductor device which is interfaceable with external at a voltage higher than in the internal of the semiconductor device, and which allows low power consumption without decreasing the operation speed in a low voltage operation.
To securely and easily prevent the breakdown of the transistors to thereby improve the reliability of the device, the following measures can be taken.
For example, in one embodiment of the level shift circuit of the third aspect of the invention, the second and third first-conductivity-type MOS transistors and the second and third second-conductivity-type MOS transistors, to which a relatively large voltage is applied, each have a gate oxide larger in film thickness than gate oxides of the first first-conductivity-type MOS transistor and the first second-conductivity-type MOS transistor of the inverter circuit, to which a relatively low voltage is applied.
In another embodiment, the drain of the second first-conductivity-type MOS transistor and the drain of the second second-conductivity-type MOS transistor are connected to each other via one or more fourth second-conductivity-type MOS transistors, and the drain of the third first-conductivity-type MOS transistor and the drain of the third second-conductivity-type MOS transistor are connected to each other via one or more fifth second-conductivity-type MOS transistors. Each of the fourth and fifth second-conductivity-type MOS transistors has its gate and drain connected to each other.
In a further embodiment, the drain of the second first-conductivity-type MOS transistor and the drain of the second second-conductivity-type MOS transistor are connected to each other via one or more series-connected diodes, with an anode of each diode directed toward the drain of the second second-conductivity-type MOS transistor, and with a cathode thereof directed toward the drain of the second first-conductivity-type MOS transistor, and the drain of the third first-conductivity-type MOS transistor and the drain of the third second-conductivity-type MOS transistor are connected to each other via one or more series-connected diodes, with an anode of each diode directed toward the drain of the third second-conductivity-type MOS transistor, and with a cathode thereof directed toward the drain of the third first-conductivity-type MOS transistor.
The immediately above two embodiments intend to avoid application of a high voltage to the drains of the second and third first-conductivity-type MOS transistors which receive a low voltage at their respective gates.
In still another embodiment, the second power supply and the source of the second second-conductivity-type MOS transistor are connected to each other via one or more series-connected diodes, with an anode of each diode directed toward the second power supply, and with a cathode thereof directed toward the source of the second second-conductivity-type MOS transistor, and the second power supply and the source of the third second-conductivity-type MOS transistor are connected to each other via one or more series-connected diodes, with an anode of each diode directed toward the second power supply and with a cathode thereof directed toward the source of the third second-conductivity-type MOS transistor. This embodiment also intends to avoid application of a high voltage to the drains of the second and third first-conductivity-type MOS transistors which receive a low voltage at their respective gates. Also, this embodiment eliminates MOS transistors that have a thick gate oxide, which is difficult to form, and that have a low threshold. Thus, the MOS transistors of the level shift circuit can be formed in a simplified process.
Other objects, features and advantages of the present invention will be obvious from the following description.